<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
<meta http-equiv="X-UA-Compatible" content="IE=9"/>
<meta name="generator" content="Doxygen 1.8.5"/>
<title>qspips: xqspips_hw.h File Reference</title>
<link href="tabs.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="jquery.js"></script>
<script type="text/javascript" src="dynsections.js"></script>
<link href="navtree.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="resize.js"></script>
<script type="text/javascript" src="navtree.js"></script>
<script type="text/javascript">
  $(document).ready(initResizable);
  $(window).load(resizeHeight);
</script>
<link href="doxygen.css" rel="stylesheet" type="text/css" />
<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
</head>
<body>
<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
<div id="titlearea">
<table cellspacing="0" cellpadding="0">
 <tbody>
 <tr style="height: 56px;">
  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.png"/></td>
  <td style="padding-left: 0.5em;">
   <div id="projectname">qspips
   </div>
   <div id="projectbrief">Vitis Drivers API Documentation</div>
  </td>
 </tr>
 </tbody>
</table>
</div>
<!-- end header part -->
<!-- Generated by Doxygen 1.8.5 -->
  <div id="navrow1" class="tabs">
    <ul class="tablist">
      <li><a href="index.html"><span>Overview</span></a></li>
      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
      <li><a href="globals.html"><span>APIs</span></a></li>
      <li><a href="files.html"><span>File&#160;List</span></a></li>
      <li><a href="pages.html"><span>Examples</span></a></li>
    </ul>
  </div>
</div><!-- top -->
<div id="side-nav" class="ui-resizable side-nav-resizable">
  <div id="nav-tree">
    <div id="nav-tree-contents">
      <div id="nav-sync" class="sync"></div>
    </div>
  </div>
  <div id="splitbar" style="-moz-user-select:none;" 
       class="ui-resizable-handle">
  </div>
</div>
<script type="text/javascript">
$(document).ready(function(){initNavTree('xqspips__hw_8h.html','');});
</script>
<div id="doc-content">
<div class="header">
  <div class="summary">
<a href="#define-members">Macros</a> &#124;
<a href="#func-members">Functions</a>  </div>
  <div class="headertitle">
<div class="title">xqspips_hw.h File Reference</div>  </div>
</div><!--header-->
<div class="contents">
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ga816dc349df40d377cb0b08d93bee37d2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga816dc349df40d377cb0b08d93bee37d2">XQspiPs_ReadReg</a>(BaseAddress, RegOffset)&#160;&#160;&#160;XQspiPs_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:ga816dc349df40d377cb0b08d93bee37d2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read a register.  <a href="group__qspips.html#ga816dc349df40d377cb0b08d93bee37d2">More...</a><br/></td></tr>
<tr class="separator:ga816dc349df40d377cb0b08d93bee37d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0d50616771e04824af465a0f078a7ebb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga0d50616771e04824af465a0f078a7ebb">XQspiPs_WriteReg</a>(BaseAddress, RegOffset, RegisterValue)&#160;&#160;&#160;XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))</td></tr>
<tr class="memdesc:ga0d50616771e04824af465a0f078a7ebb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write to a register.  <a href="group__qspips.html#ga0d50616771e04824af465a0f078a7ebb">More...</a><br/></td></tr>
<tr class="separator:ga0d50616771e04824af465a0f078a7ebb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register Map</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register offsets from the base address of an QSPI device. </p>
</div></td></tr>
<tr class="memitem:gad65b0a99e7acd5b73ef96245cabee22b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gad65b0a99e7acd5b73ef96245cabee22b">XQSPIPS_CR_OFFSET</a>&#160;&#160;&#160;0x00</td></tr>
<tr class="memdesc:gad65b0a99e7acd5b73ef96245cabee22b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configuration Register.  <a href="group__qspips.html#gad65b0a99e7acd5b73ef96245cabee22b">More...</a><br/></td></tr>
<tr class="separator:gad65b0a99e7acd5b73ef96245cabee22b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga932c802186fcabf52f50881159028535"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga932c802186fcabf52f50881159028535">XQSPIPS_SR_OFFSET</a>&#160;&#160;&#160;0x04</td></tr>
<tr class="memdesc:ga932c802186fcabf52f50881159028535"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Status.  <a href="group__qspips.html#ga932c802186fcabf52f50881159028535">More...</a><br/></td></tr>
<tr class="separator:ga932c802186fcabf52f50881159028535"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaeb7277c4dc92141976f2a238c80b3a21"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gaeb7277c4dc92141976f2a238c80b3a21">XQSPIPS_IER_OFFSET</a>&#160;&#160;&#160;0x08</td></tr>
<tr class="memdesc:gaeb7277c4dc92141976f2a238c80b3a21"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Enable.  <a href="group__qspips.html#gaeb7277c4dc92141976f2a238c80b3a21">More...</a><br/></td></tr>
<tr class="separator:gaeb7277c4dc92141976f2a238c80b3a21"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0273dd38f06363ce19a473304589ca26"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga0273dd38f06363ce19a473304589ca26">XQSPIPS_IDR_OFFSET</a>&#160;&#160;&#160;0x0c</td></tr>
<tr class="memdesc:ga0273dd38f06363ce19a473304589ca26"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Disable.  <a href="group__qspips.html#ga0273dd38f06363ce19a473304589ca26">More...</a><br/></td></tr>
<tr class="separator:ga0273dd38f06363ce19a473304589ca26"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad146aae5ec2398afb5a876f6aff16c60"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gad146aae5ec2398afb5a876f6aff16c60">XQSPIPS_IMR_OFFSET</a>&#160;&#160;&#160;0x10</td></tr>
<tr class="memdesc:gad146aae5ec2398afb5a876f6aff16c60"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Enabled Mask.  <a href="group__qspips.html#gad146aae5ec2398afb5a876f6aff16c60">More...</a><br/></td></tr>
<tr class="separator:gad146aae5ec2398afb5a876f6aff16c60"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadeb61bbc1b66a0fde033664cfee4fd30"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gadeb61bbc1b66a0fde033664cfee4fd30">XQSPIPS_ER_OFFSET</a>&#160;&#160;&#160;0x14</td></tr>
<tr class="memdesc:gadeb61bbc1b66a0fde033664cfee4fd30"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable/Disable Register.  <a href="group__qspips.html#gadeb61bbc1b66a0fde033664cfee4fd30">More...</a><br/></td></tr>
<tr class="separator:gadeb61bbc1b66a0fde033664cfee4fd30"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga108ac25b6c44eb9e0babd1a7948e18cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga108ac25b6c44eb9e0babd1a7948e18cc">XQSPIPS_DR_OFFSET</a>&#160;&#160;&#160;0x18</td></tr>
<tr class="memdesc:ga108ac25b6c44eb9e0babd1a7948e18cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Delay Register.  <a href="group__qspips.html#ga108ac25b6c44eb9e0babd1a7948e18cc">More...</a><br/></td></tr>
<tr class="separator:ga108ac25b6c44eb9e0babd1a7948e18cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5dda022acf4337554d3db261663dcc29"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga5dda022acf4337554d3db261663dcc29">XQSPIPS_TXD_00_OFFSET</a>&#160;&#160;&#160;0x1C</td></tr>
<tr class="memdesc:ga5dda022acf4337554d3db261663dcc29"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit 4-byte inst/data.  <a href="group__qspips.html#ga5dda022acf4337554d3db261663dcc29">More...</a><br/></td></tr>
<tr class="separator:ga5dda022acf4337554d3db261663dcc29"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9e202889f9544e37c4ef76f8ded6df7f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga9e202889f9544e37c4ef76f8ded6df7f">XQSPIPS_RXD_OFFSET</a>&#160;&#160;&#160;0x20</td></tr>
<tr class="memdesc:ga9e202889f9544e37c4ef76f8ded6df7f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Receive Register.  <a href="group__qspips.html#ga9e202889f9544e37c4ef76f8ded6df7f">More...</a><br/></td></tr>
<tr class="separator:ga9e202889f9544e37c4ef76f8ded6df7f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0781d2328e59158090ba44294f6ca8d1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga0781d2328e59158090ba44294f6ca8d1">XQSPIPS_SICR_OFFSET</a>&#160;&#160;&#160;0x24</td></tr>
<tr class="memdesc:ga0781d2328e59158090ba44294f6ca8d1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Idle Count.  <a href="group__qspips.html#ga0781d2328e59158090ba44294f6ca8d1">More...</a><br/></td></tr>
<tr class="separator:ga0781d2328e59158090ba44294f6ca8d1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaca82abc3f1f75efb2d1b6d67a735bb23"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gaca82abc3f1f75efb2d1b6d67a735bb23">XQSPIPS_TXWR_OFFSET</a>&#160;&#160;&#160;0x28</td></tr>
<tr class="memdesc:gaca82abc3f1f75efb2d1b6d67a735bb23"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit FIFO Watermark.  <a href="group__qspips.html#gaca82abc3f1f75efb2d1b6d67a735bb23">More...</a><br/></td></tr>
<tr class="separator:gaca82abc3f1f75efb2d1b6d67a735bb23"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacfe5eff35c496b0555437eae756ab3ba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gacfe5eff35c496b0555437eae756ab3ba">XQSPIPS_RXWR_OFFSET</a>&#160;&#160;&#160;0x2C</td></tr>
<tr class="memdesc:gacfe5eff35c496b0555437eae756ab3ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive FIFO Watermark.  <a href="group__qspips.html#gacfe5eff35c496b0555437eae756ab3ba">More...</a><br/></td></tr>
<tr class="separator:gacfe5eff35c496b0555437eae756ab3ba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3829bec1dd9c175514efb6ff3bdd8a85"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga3829bec1dd9c175514efb6ff3bdd8a85">XQSPIPS_GPIO_OFFSET</a>&#160;&#160;&#160;0x30</td></tr>
<tr class="memdesc:ga3829bec1dd9c175514efb6ff3bdd8a85"><td class="mdescLeft">&#160;</td><td class="mdescRight">GPIO Register.  <a href="group__qspips.html#ga3829bec1dd9c175514efb6ff3bdd8a85">More...</a><br/></td></tr>
<tr class="separator:ga3829bec1dd9c175514efb6ff3bdd8a85"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabb6e04970bc1755d9f1d67e155042bff"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gabb6e04970bc1755d9f1d67e155042bff">XQSPIPS_LPBK_DLY_ADJ_OFFSET</a>&#160;&#160;&#160;0x38</td></tr>
<tr class="memdesc:gabb6e04970bc1755d9f1d67e155042bff"><td class="mdescLeft">&#160;</td><td class="mdescRight">Loopback Delay Adjust Reg.  <a href="group__qspips.html#gabb6e04970bc1755d9f1d67e155042bff">More...</a><br/></td></tr>
<tr class="separator:gabb6e04970bc1755d9f1d67e155042bff"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad5bf76639c42c131bf81ac80c3e21ec8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gad5bf76639c42c131bf81ac80c3e21ec8">XQSPIPS_TXD_01_OFFSET</a>&#160;&#160;&#160;0x80</td></tr>
<tr class="memdesc:gad5bf76639c42c131bf81ac80c3e21ec8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit 1-byte inst.  <a href="group__qspips.html#gad5bf76639c42c131bf81ac80c3e21ec8">More...</a><br/></td></tr>
<tr class="separator:gad5bf76639c42c131bf81ac80c3e21ec8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga67b841cfcf0b4c0ed0a3bd156cb740cf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga67b841cfcf0b4c0ed0a3bd156cb740cf">XQSPIPS_TXD_10_OFFSET</a>&#160;&#160;&#160;0x84</td></tr>
<tr class="memdesc:ga67b841cfcf0b4c0ed0a3bd156cb740cf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit 2-byte inst.  <a href="group__qspips.html#ga67b841cfcf0b4c0ed0a3bd156cb740cf">More...</a><br/></td></tr>
<tr class="separator:ga67b841cfcf0b4c0ed0a3bd156cb740cf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga30f47aecc238b9f22fd577c3c13d5544"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga30f47aecc238b9f22fd577c3c13d5544">XQSPIPS_TXD_11_OFFSET</a>&#160;&#160;&#160;0x88</td></tr>
<tr class="memdesc:ga30f47aecc238b9f22fd577c3c13d5544"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit 3-byte inst.  <a href="group__qspips.html#ga30f47aecc238b9f22fd577c3c13d5544">More...</a><br/></td></tr>
<tr class="separator:ga30f47aecc238b9f22fd577c3c13d5544"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga569d8bbdf1473234ab9d067d46c5a454"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga569d8bbdf1473234ab9d067d46c5a454">XQSPIPS_LQSPI_CR_OFFSET</a>&#160;&#160;&#160;0xA0</td></tr>
<tr class="memdesc:ga569d8bbdf1473234ab9d067d46c5a454"><td class="mdescLeft">&#160;</td><td class="mdescRight">Linear QSPI config register.  <a href="group__qspips.html#ga569d8bbdf1473234ab9d067d46c5a454">More...</a><br/></td></tr>
<tr class="separator:ga569d8bbdf1473234ab9d067d46c5a454"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadab922905ac2ae980d7b094a62e5aafc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gadab922905ac2ae980d7b094a62e5aafc">XQSPIPS_LQSPI_SR_OFFSET</a>&#160;&#160;&#160;0xA4</td></tr>
<tr class="memdesc:gadab922905ac2ae980d7b094a62e5aafc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Linear QSPI status register.  <a href="group__qspips.html#gadab922905ac2ae980d7b094a62e5aafc">More...</a><br/></td></tr>
<tr class="separator:gadab922905ac2ae980d7b094a62e5aafc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa84ef0f51f3ddc18f9d7d684dfa5f924"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gaa84ef0f51f3ddc18f9d7d684dfa5f924">XQSPIPS_MOD_ID_OFFSET</a>&#160;&#160;&#160;0xFC</td></tr>
<tr class="memdesc:gaa84ef0f51f3ddc18f9d7d684dfa5f924"><td class="mdescLeft">&#160;</td><td class="mdescRight">Module ID register.  <a href="group__qspips.html#gaa84ef0f51f3ddc18f9d7d684dfa5f924">More...</a><br/></td></tr>
<tr class="separator:gaa84ef0f51f3ddc18f9d7d684dfa5f924"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Configuration Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains various control bits that affect the operation of the QSPI device.</p>
<p>Read/Write. </p>
</div></td></tr>
<tr class="memitem:ga7fdb4394bae580ea63ef74ff202713f9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga7fdb4394bae580ea63ef74ff202713f9">XQSPIPS_CR_IFMODE_MASK</a>&#160;&#160;&#160;0x80000000</td></tr>
<tr class="memdesc:ga7fdb4394bae580ea63ef74ff202713f9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flash mem interface mode.  <a href="group__qspips.html#ga7fdb4394bae580ea63ef74ff202713f9">More...</a><br/></td></tr>
<tr class="separator:ga7fdb4394bae580ea63ef74ff202713f9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab4f388c3e262a39963914757c9535ffd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gab4f388c3e262a39963914757c9535ffd">XQSPIPS_CR_ENDIAN_MASK</a>&#160;&#160;&#160;0x04000000</td></tr>
<tr class="memdesc:gab4f388c3e262a39963914757c9535ffd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tx/Rx FIFO endianness.  <a href="group__qspips.html#gab4f388c3e262a39963914757c9535ffd">More...</a><br/></td></tr>
<tr class="separator:gab4f388c3e262a39963914757c9535ffd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga153c93f73abd1240e238aa0fe5bff099"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga153c93f73abd1240e238aa0fe5bff099">XQSPIPS_CR_MANSTRT_MASK</a>&#160;&#160;&#160;0x00010000</td></tr>
<tr class="memdesc:ga153c93f73abd1240e238aa0fe5bff099"><td class="mdescLeft">&#160;</td><td class="mdescRight">Manual Transmission Start.  <a href="group__qspips.html#ga153c93f73abd1240e238aa0fe5bff099">More...</a><br/></td></tr>
<tr class="separator:ga153c93f73abd1240e238aa0fe5bff099"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadc8a72b569bec261d09d0b503687f5c3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gadc8a72b569bec261d09d0b503687f5c3">XQSPIPS_CR_MANSTRTEN_MASK</a>&#160;&#160;&#160;0x00008000</td></tr>
<tr class="memdesc:gadc8a72b569bec261d09d0b503687f5c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Manual Transmission Start Enable.  <a href="group__qspips.html#gadc8a72b569bec261d09d0b503687f5c3">More...</a><br/></td></tr>
<tr class="separator:gadc8a72b569bec261d09d0b503687f5c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab8c609b8289ed6b9b7fb337477bba0db"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gab8c609b8289ed6b9b7fb337477bba0db">XQSPIPS_CR_SSFORCE_MASK</a>&#160;&#160;&#160;0x00004000</td></tr>
<tr class="memdesc:gab8c609b8289ed6b9b7fb337477bba0db"><td class="mdescLeft">&#160;</td><td class="mdescRight">Force Slave Select.  <a href="group__qspips.html#gab8c609b8289ed6b9b7fb337477bba0db">More...</a><br/></td></tr>
<tr class="separator:gab8c609b8289ed6b9b7fb337477bba0db"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga18805dc0789d5e4bfba04ea85ce1395e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga18805dc0789d5e4bfba04ea85ce1395e">XQSPIPS_CR_SSCTRL_MASK</a>&#160;&#160;&#160;0x00000400</td></tr>
<tr class="memdesc:ga18805dc0789d5e4bfba04ea85ce1395e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Select Decode.  <a href="group__qspips.html#ga18805dc0789d5e4bfba04ea85ce1395e">More...</a><br/></td></tr>
<tr class="separator:ga18805dc0789d5e4bfba04ea85ce1395e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadd25c288ae539e4c553e6d83c2f8b9e8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gadd25c288ae539e4c553e6d83c2f8b9e8">XQSPIPS_CR_SSCTRL_SHIFT</a>&#160;&#160;&#160;10</td></tr>
<tr class="memdesc:gadd25c288ae539e4c553e6d83c2f8b9e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Select Decode shift.  <a href="group__qspips.html#gadd25c288ae539e4c553e6d83c2f8b9e8">More...</a><br/></td></tr>
<tr class="separator:gadd25c288ae539e4c553e6d83c2f8b9e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8c0a0df06417ac7c6ca6284bd5ec37b6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga8c0a0df06417ac7c6ca6284bd5ec37b6">XQSPIPS_CR_DATA_SZ_MASK</a>&#160;&#160;&#160;0x000000C0</td></tr>
<tr class="memdesc:ga8c0a0df06417ac7c6ca6284bd5ec37b6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Size of word to be transferred.  <a href="group__qspips.html#ga8c0a0df06417ac7c6ca6284bd5ec37b6">More...</a><br/></td></tr>
<tr class="separator:ga8c0a0df06417ac7c6ca6284bd5ec37b6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaada7d5e9fd8a0575f83c54d32155ccd2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gaada7d5e9fd8a0575f83c54d32155ccd2">XQSPIPS_CR_PRESC_MASK</a>&#160;&#160;&#160;0x00000038</td></tr>
<tr class="memdesc:gaada7d5e9fd8a0575f83c54d32155ccd2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prescaler Setting.  <a href="group__qspips.html#gaada7d5e9fd8a0575f83c54d32155ccd2">More...</a><br/></td></tr>
<tr class="separator:gaada7d5e9fd8a0575f83c54d32155ccd2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga383bb44aa6dcae975de138577e837543"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga383bb44aa6dcae975de138577e837543">XQSPIPS_CR_PRESC_SHIFT</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:ga383bb44aa6dcae975de138577e837543"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prescaler shift.  <a href="group__qspips.html#ga383bb44aa6dcae975de138577e837543">More...</a><br/></td></tr>
<tr class="separator:ga383bb44aa6dcae975de138577e837543"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7efbd780e81bffc209d57e4124c95499"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga7efbd780e81bffc209d57e4124c95499">XQSPIPS_CR_PRESC_MAXIMUM</a>&#160;&#160;&#160;0x07</td></tr>
<tr class="memdesc:ga7efbd780e81bffc209d57e4124c95499"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prescaler maximum value.  <a href="group__qspips.html#ga7efbd780e81bffc209d57e4124c95499">More...</a><br/></td></tr>
<tr class="separator:ga7efbd780e81bffc209d57e4124c95499"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae928c099fd4d1427d83309550464d589"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gae928c099fd4d1427d83309550464d589">XQSPIPS_CR_CPHA_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gae928c099fd4d1427d83309550464d589"><td class="mdescLeft">&#160;</td><td class="mdescRight">Phase Configuration.  <a href="group__qspips.html#gae928c099fd4d1427d83309550464d589">More...</a><br/></td></tr>
<tr class="separator:gae928c099fd4d1427d83309550464d589"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0d462dc931e6c9d1ed845190b1dd18a7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga0d462dc931e6c9d1ed845190b1dd18a7">XQSPIPS_CR_CPOL_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ga0d462dc931e6c9d1ed845190b1dd18a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Polarity Configuration.  <a href="group__qspips.html#ga0d462dc931e6c9d1ed845190b1dd18a7">More...</a><br/></td></tr>
<tr class="separator:ga0d462dc931e6c9d1ed845190b1dd18a7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga64c12fb196b1c07f70eae117ff1b0a20"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga64c12fb196b1c07f70eae117ff1b0a20">XQSPIPS_CR_MSTREN_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga64c12fb196b1c07f70eae117ff1b0a20"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master Mode Enable.  <a href="group__qspips.html#ga64c12fb196b1c07f70eae117ff1b0a20">More...</a><br/></td></tr>
<tr class="separator:ga64c12fb196b1c07f70eae117ff1b0a20"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8e37eb5b65d43582a068c281fcb33e44"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga8e37eb5b65d43582a068c281fcb33e44">XQSPIPS_CR_HOLD_B_MASK</a>&#160;&#160;&#160;0x00080000</td></tr>
<tr class="memdesc:ga8e37eb5b65d43582a068c281fcb33e44"><td class="mdescLeft">&#160;</td><td class="mdescRight">HOLD_B Pin Drive Enable.  <a href="group__qspips.html#ga8e37eb5b65d43582a068c281fcb33e44">More...</a><br/></td></tr>
<tr class="separator:ga8e37eb5b65d43582a068c281fcb33e44"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac8c3ff005783e08e09beb3c8ea030f14"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gac8c3ff005783e08e09beb3c8ea030f14">XQSPIPS_CR_REF_CLK_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:gac8c3ff005783e08e09beb3c8ea030f14"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ref clk bit - should be 0.  <a href="group__qspips.html#gac8c3ff005783e08e09beb3c8ea030f14">More...</a><br/></td></tr>
<tr class="separator:gac8c3ff005783e08e09beb3c8ea030f14"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab4c29699eb9aa0a81e5ce1441c309ca9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab4c29699eb9aa0a81e5ce1441c309ca9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPS_CR_RESET_MASK_SET</b></td></tr>
<tr class="separator:gab4c29699eb9aa0a81e5ce1441c309ca9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab92d1006b5c167d5d8ed7b1e9150bab3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab92d1006b5c167d5d8ed7b1e9150bab3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPS_CR_RESET_MASK_CLR</b></td></tr>
<tr class="separator:gab92d1006b5c167d5d8ed7b1e9150bab3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">QSPI Interrupt Registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p><b>QSPI Status Register</b></p>
<p>This register holds the interrupt status flags for an QSPI device. Some of the flags are level triggered, which means that they are set as long as the interrupt condition exists. Other flags are edge triggered, which means they are set once the interrupt condition occurs and remain set until they are cleared by software. The interrupts are cleared by writing a '1' to the interrupt bit position in the Status Register. Read/Write.</p>
<p><b>QSPI Interrupt Enable Register</b></p>
<p>This register is used to enable chosen interrupts for an QSPI device. Writing a '1' to a bit in this register sets the corresponding bit in the QSPI Interrupt Mask register. Write only.</p>
<p><b>QSPI Interrupt Disable Register </b></p>
<p>This register is used to disable chosen interrupts for an QSPI device. Writing a '1' to a bit in this register clears the corresponding bit in the QSPI Interrupt Mask register. Write only.</p>
<p><b>QSPI Interrupt Mask Register</b></p>
<p>This register shows the enabled/disabled interrupts of an QSPI device. Read only.</p>
<p>All four registers have the same bit definitions. They are only defined once for each of the Interrupt Enable Register, Interrupt Disable Register, Interrupt Mask Register, and Channel Interrupt Status Register </p>
</div></td></tr>
<tr class="memitem:ga46b985ce1ff37d75727ebaa8d95004ee"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga46b985ce1ff37d75727ebaa8d95004ee">XQSPIPS_IXR_TXUF_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:ga46b985ce1ff37d75727ebaa8d95004ee"><td class="mdescLeft">&#160;</td><td class="mdescRight">QSPI Tx FIFO Underflow.  <a href="group__qspips.html#ga46b985ce1ff37d75727ebaa8d95004ee">More...</a><br/></td></tr>
<tr class="separator:ga46b985ce1ff37d75727ebaa8d95004ee"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaeaf6b9eec8bb18a8aea981f5ba596179"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gaeaf6b9eec8bb18a8aea981f5ba596179">XQSPIPS_IXR_RXFULL_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:gaeaf6b9eec8bb18a8aea981f5ba596179"><td class="mdescLeft">&#160;</td><td class="mdescRight">QSPI Rx FIFO Full.  <a href="group__qspips.html#gaeaf6b9eec8bb18a8aea981f5ba596179">More...</a><br/></td></tr>
<tr class="separator:gaeaf6b9eec8bb18a8aea981f5ba596179"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaffcc35360d77f07d56312cf208ddc4c3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gaffcc35360d77f07d56312cf208ddc4c3">XQSPIPS_IXR_RXNEMPTY_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:gaffcc35360d77f07d56312cf208ddc4c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">QSPI Rx FIFO Not Empty.  <a href="group__qspips.html#gaffcc35360d77f07d56312cf208ddc4c3">More...</a><br/></td></tr>
<tr class="separator:gaffcc35360d77f07d56312cf208ddc4c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga023456cea2736c8018b5dc3e2200b2ee"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga023456cea2736c8018b5dc3e2200b2ee">XQSPIPS_IXR_TXFULL_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga023456cea2736c8018b5dc3e2200b2ee"><td class="mdescLeft">&#160;</td><td class="mdescRight">QSPI Tx FIFO Full.  <a href="group__qspips.html#ga023456cea2736c8018b5dc3e2200b2ee">More...</a><br/></td></tr>
<tr class="separator:ga023456cea2736c8018b5dc3e2200b2ee"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga491641b423fa08099b6f14890e42079f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga491641b423fa08099b6f14890e42079f">XQSPIPS_IXR_TXOW_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga491641b423fa08099b6f14890e42079f"><td class="mdescLeft">&#160;</td><td class="mdescRight">QSPI Tx FIFO Overwater.  <a href="group__qspips.html#ga491641b423fa08099b6f14890e42079f">More...</a><br/></td></tr>
<tr class="separator:ga491641b423fa08099b6f14890e42079f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga62fc17aae53cac9cc489e91c4a9b1602"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga62fc17aae53cac9cc489e91c4a9b1602">XQSPIPS_IXR_RXOVR_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga62fc17aae53cac9cc489e91c4a9b1602"><td class="mdescLeft">&#160;</td><td class="mdescRight">QSPI Rx FIFO Overrun.  <a href="group__qspips.html#ga62fc17aae53cac9cc489e91c4a9b1602">More...</a><br/></td></tr>
<tr class="separator:ga62fc17aae53cac9cc489e91c4a9b1602"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga20a2334064dc754e55bcc1bf3d586e3d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga20a2334064dc754e55bcc1bf3d586e3d">XQSPIPS_IXR_DFLT_MASK</a>&#160;&#160;&#160;0x00000025</td></tr>
<tr class="memdesc:ga20a2334064dc754e55bcc1bf3d586e3d"><td class="mdescLeft">&#160;</td><td class="mdescRight">QSPI default interrupts mask.  <a href="group__qspips.html#ga20a2334064dc754e55bcc1bf3d586e3d">More...</a><br/></td></tr>
<tr class="separator:ga20a2334064dc754e55bcc1bf3d586e3d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7d69feac74eea544a6c44f0528d617c6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga7d69feac74eea544a6c44f0528d617c6">XQSPIPS_IXR_WR_TO_CLR_MASK</a>&#160;&#160;&#160;0x00000041</td></tr>
<tr class="memdesc:ga7d69feac74eea544a6c44f0528d617c6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupts which need write to clear.  <a href="group__qspips.html#ga7d69feac74eea544a6c44f0528d617c6">More...</a><br/></td></tr>
<tr class="separator:ga7d69feac74eea544a6c44f0528d617c6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf23adee5f63eadcc9d7811b0ae125573"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gaf23adee5f63eadcc9d7811b0ae125573">XQSPIPS_ISR_RESET_STATE</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gaf23adee5f63eadcc9d7811b0ae125573"><td class="mdescLeft">&#160;</td><td class="mdescRight">Default to tx/rx empty.  <a href="group__qspips.html#gaf23adee5f63eadcc9d7811b0ae125573">More...</a><br/></td></tr>
<tr class="separator:gaf23adee5f63eadcc9d7811b0ae125573"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga40777e9e6b84d8b83cdbac816f2f46f4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga40777e9e6b84d8b83cdbac816f2f46f4">XQSPIPS_IXR_DISABLE_ALL</a>&#160;&#160;&#160;0x0000007D</td></tr>
<tr class="memdesc:ga40777e9e6b84d8b83cdbac816f2f46f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable all interrupts.  <a href="group__qspips.html#ga40777e9e6b84d8b83cdbac816f2f46f4">More...</a><br/></td></tr>
<tr class="separator:ga40777e9e6b84d8b83cdbac816f2f46f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Enable Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register is used to enable or disable an QSPI device.</p>
<p>Read/Write </p>
</div></td></tr>
<tr class="memitem:ga59b8080014041bb088c8fd28a2154b8d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga59b8080014041bb088c8fd28a2154b8d">XQSPIPS_ER_ENABLE_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga59b8080014041bb088c8fd28a2154b8d"><td class="mdescLeft">&#160;</td><td class="mdescRight">QSPI Enable Bit Mask.  <a href="group__qspips.html#ga59b8080014041bb088c8fd28a2154b8d">More...</a><br/></td></tr>
<tr class="separator:ga59b8080014041bb088c8fd28a2154b8d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Delay Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register is used to program timing delays in slave mode.</p>
<p>Read/Write </p>
</div></td></tr>
<tr class="memitem:gabc227ea7c06b95d6f70c1f1b91674514"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gabc227ea7c06b95d6f70c1f1b91674514">XQSPIPS_DR_NSS_MASK</a>&#160;&#160;&#160;0xFF000000</td></tr>
<tr class="memdesc:gabc227ea7c06b95d6f70c1f1b91674514"><td class="mdescLeft">&#160;</td><td class="mdescRight">Delay to de-assert slave select between two words mask.  <a href="group__qspips.html#gabc227ea7c06b95d6f70c1f1b91674514">More...</a><br/></td></tr>
<tr class="separator:gabc227ea7c06b95d6f70c1f1b91674514"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5f8585aa21a78dbeeb3501b3a2be232f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga5f8585aa21a78dbeeb3501b3a2be232f">XQSPIPS_DR_NSS_SHIFT</a>&#160;&#160;&#160;24</td></tr>
<tr class="memdesc:ga5f8585aa21a78dbeeb3501b3a2be232f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Delay to de-assert slave select between two words shift.  <a href="group__qspips.html#ga5f8585aa21a78dbeeb3501b3a2be232f">More...</a><br/></td></tr>
<tr class="separator:ga5f8585aa21a78dbeeb3501b3a2be232f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga13ae52f0fa79506212aae52080096177"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga13ae52f0fa79506212aae52080096177">XQSPIPS_DR_BTWN_MASK</a>&#160;&#160;&#160;0x00FF0000</td></tr>
<tr class="memdesc:ga13ae52f0fa79506212aae52080096177"><td class="mdescLeft">&#160;</td><td class="mdescRight">Delay Between Transfers mask.  <a href="group__qspips.html#ga13ae52f0fa79506212aae52080096177">More...</a><br/></td></tr>
<tr class="separator:ga13ae52f0fa79506212aae52080096177"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3f210c67ccbc40aca99fdeeefb6a456b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga3f210c67ccbc40aca99fdeeefb6a456b">XQSPIPS_DR_BTWN_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga3f210c67ccbc40aca99fdeeefb6a456b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Delay Between Transfers shift.  <a href="group__qspips.html#ga3f210c67ccbc40aca99fdeeefb6a456b">More...</a><br/></td></tr>
<tr class="separator:ga3f210c67ccbc40aca99fdeeefb6a456b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga993b6ddfc938d8cc0addfa76e50fa20c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga993b6ddfc938d8cc0addfa76e50fa20c">XQSPIPS_DR_AFTER_MASK</a>&#160;&#160;&#160;0x0000FF00</td></tr>
<tr class="memdesc:ga993b6ddfc938d8cc0addfa76e50fa20c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Delay After Transfers mask.  <a href="group__qspips.html#ga993b6ddfc938d8cc0addfa76e50fa20c">More...</a><br/></td></tr>
<tr class="separator:ga993b6ddfc938d8cc0addfa76e50fa20c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga75799fb67be08680e1111f9e0657051b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga75799fb67be08680e1111f9e0657051b">XQSPIPS_DR_AFTER_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:ga75799fb67be08680e1111f9e0657051b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Delay After Transfers shift.  <a href="group__qspips.html#ga75799fb67be08680e1111f9e0657051b">More...</a><br/></td></tr>
<tr class="separator:ga75799fb67be08680e1111f9e0657051b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5623dd8f755d70760b91137ee24f3116"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga5623dd8f755d70760b91137ee24f3116">XQSPIPS_DR_INIT_MASK</a>&#160;&#160;&#160;0x000000FF</td></tr>
<tr class="memdesc:ga5623dd8f755d70760b91137ee24f3116"><td class="mdescLeft">&#160;</td><td class="mdescRight">Delay Initially mask.  <a href="group__qspips.html#ga5623dd8f755d70760b91137ee24f3116">More...</a><br/></td></tr>
<tr class="separator:ga5623dd8f755d70760b91137ee24f3116"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Slave Idle Count Registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register defines the number of pclk cycles the slave waits for a the QSPI clock to become stable in quiescent state before it can detect the start of the next transfer in CPHA = 1 mode.</p>
<p>Read/Write </p>
</div></td></tr>
<tr class="memitem:gaf23ade3775cacdcf55f592c7b63156ef"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gaf23ade3775cacdcf55f592c7b63156ef">XQSPIPS_SICR_MASK</a>&#160;&#160;&#160;0x000000FF</td></tr>
<tr class="memdesc:gaf23ade3775cacdcf55f592c7b63156ef"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Idle Count Mask.  <a href="group__qspips.html#gaf23ade3775cacdcf55f592c7b63156ef">More...</a><br/></td></tr>
<tr class="separator:gaf23ade3775cacdcf55f592c7b63156ef"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Transmit FIFO Watermark Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register defines the watermark setting for the Transmit FIFO. </p>
</div></td></tr>
<tr class="memitem:gadd8b2b1507bf4ad065d64832baa398aa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gadd8b2b1507bf4ad065d64832baa398aa">XQSPIPS_TXWR_MASK</a>&#160;&#160;&#160;0x0000003F</td></tr>
<tr class="memdesc:gadd8b2b1507bf4ad065d64832baa398aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit Watermark Mask.  <a href="group__qspips.html#gadd8b2b1507bf4ad065d64832baa398aa">More...</a><br/></td></tr>
<tr class="separator:gadd8b2b1507bf4ad065d64832baa398aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaef912da3bdebe9cb54c18472c0b0b50c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gaef912da3bdebe9cb54c18472c0b0b50c">XQSPIPS_TXWR_RESET_VALUE</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:gaef912da3bdebe9cb54c18472c0b0b50c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit Watermark register reset value.  <a href="group__qspips.html#gaef912da3bdebe9cb54c18472c0b0b50c">More...</a><br/></td></tr>
<tr class="separator:gaef912da3bdebe9cb54c18472c0b0b50c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Receive FIFO Watermark Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register defines the watermark setting for the Receive FIFO. </p>
</div></td></tr>
<tr class="memitem:ga72c315000e6adebb4eccac4f7ccd3ec3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga72c315000e6adebb4eccac4f7ccd3ec3">XQSPIPS_RXWR_MASK</a>&#160;&#160;&#160;0x0000003F</td></tr>
<tr class="memdesc:ga72c315000e6adebb4eccac4f7ccd3ec3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive Watermark Mask.  <a href="group__qspips.html#ga72c315000e6adebb4eccac4f7ccd3ec3">More...</a><br/></td></tr>
<tr class="separator:ga72c315000e6adebb4eccac4f7ccd3ec3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga40a339843fea8bd9c3352c554d85ed4f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga40a339843fea8bd9c3352c554d85ed4f">XQSPIPS_RXWR_RESET_VALUE</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga40a339843fea8bd9c3352c554d85ed4f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive Watermark register reset value.  <a href="group__qspips.html#ga40a339843fea8bd9c3352c554d85ed4f">More...</a><br/></td></tr>
<tr class="separator:ga40a339843fea8bd9c3352c554d85ed4f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">FIFO Depth</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This macro provides the depth of transmit FIFO and receive FIFO. </p>
</div></td></tr>
<tr class="memitem:gaa78347b3998401c5aeebf6292ace2ce5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gaa78347b3998401c5aeebf6292ace2ce5">XQSPIPS_FIFO_DEPTH</a>&#160;&#160;&#160;63</td></tr>
<tr class="memdesc:gaa78347b3998401c5aeebf6292ace2ce5"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIFO depth (words)  <a href="group__qspips.html#gaa78347b3998401c5aeebf6292ace2ce5">More...</a><br/></td></tr>
<tr class="separator:gaa78347b3998401c5aeebf6292ace2ce5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Linear QSPI Configuration Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains various control bits that affect the operation of the Linear QSPI controller.</p>
<p>Read/Write. </p>
</div></td></tr>
<tr class="memitem:gafc4b03f8705c7c19693225d718546118"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gafc4b03f8705c7c19693225d718546118">XQSPIPS_LQSPI_CR_LINEAR_MASK</a>&#160;&#160;&#160;0x80000000</td></tr>
<tr class="memdesc:gafc4b03f8705c7c19693225d718546118"><td class="mdescLeft">&#160;</td><td class="mdescRight">LQSPI mode enable.  <a href="group__qspips.html#gafc4b03f8705c7c19693225d718546118">More...</a><br/></td></tr>
<tr class="separator:gafc4b03f8705c7c19693225d718546118"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2dad6e5df54b9e6cf4a276eaf92c6dd2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga2dad6e5df54b9e6cf4a276eaf92c6dd2">XQSPIPS_LQSPI_CR_TWO_MEM_MASK</a>&#160;&#160;&#160;0x40000000</td></tr>
<tr class="memdesc:ga2dad6e5df54b9e6cf4a276eaf92c6dd2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Both memories or one.  <a href="group__qspips.html#ga2dad6e5df54b9e6cf4a276eaf92c6dd2">More...</a><br/></td></tr>
<tr class="separator:ga2dad6e5df54b9e6cf4a276eaf92c6dd2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga18b5ef37d915313347cc7bc90d2136da"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga18b5ef37d915313347cc7bc90d2136da">XQSPIPS_LQSPI_CR_SEP_BUS_MASK</a>&#160;&#160;&#160;0x20000000</td></tr>
<tr class="memdesc:ga18b5ef37d915313347cc7bc90d2136da"><td class="mdescLeft">&#160;</td><td class="mdescRight">Separate memory bus.  <a href="group__qspips.html#ga18b5ef37d915313347cc7bc90d2136da">More...</a><br/></td></tr>
<tr class="separator:ga18b5ef37d915313347cc7bc90d2136da"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga43ea3e35e6c6a57aba2301e0a3de9e8e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga43ea3e35e6c6a57aba2301e0a3de9e8e">XQSPIPS_LQSPI_CR_U_PAGE_MASK</a>&#160;&#160;&#160;0x10000000</td></tr>
<tr class="memdesc:ga43ea3e35e6c6a57aba2301e0a3de9e8e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Upper memory page.  <a href="group__qspips.html#ga43ea3e35e6c6a57aba2301e0a3de9e8e">More...</a><br/></td></tr>
<tr class="separator:ga43ea3e35e6c6a57aba2301e0a3de9e8e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga00bf8fcd643bd848fbe928cf27bbeafe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga00bf8fcd643bd848fbe928cf27bbeafe">XQSPIPS_LQSPI_CR_MODE_EN_MASK</a>&#160;&#160;&#160;0x02000000</td></tr>
<tr class="memdesc:ga00bf8fcd643bd848fbe928cf27bbeafe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable mode bits.  <a href="group__qspips.html#ga00bf8fcd643bd848fbe928cf27bbeafe">More...</a><br/></td></tr>
<tr class="separator:ga00bf8fcd643bd848fbe928cf27bbeafe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa468fba4523d010cde533a2c4d4a8d09"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gaa468fba4523d010cde533a2c4d4a8d09">XQSPIPS_LQSPI_CR_MODE_ON_MASK</a>&#160;&#160;&#160;0x01000000</td></tr>
<tr class="memdesc:gaa468fba4523d010cde533a2c4d4a8d09"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mode on.  <a href="group__qspips.html#gaa468fba4523d010cde533a2c4d4a8d09">More...</a><br/></td></tr>
<tr class="separator:gaa468fba4523d010cde533a2c4d4a8d09"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga844b7089e30c37640c8f0fa74c875fed"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga844b7089e30c37640c8f0fa74c875fed">XQSPIPS_LQSPI_CR_MODE_BITS_MASK</a>&#160;&#160;&#160;0x00FF0000</td></tr>
<tr class="memdesc:ga844b7089e30c37640c8f0fa74c875fed"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mode value for dual I/O or quad I/O.  <a href="group__qspips.html#ga844b7089e30c37640c8f0fa74c875fed">More...</a><br/></td></tr>
<tr class="separator:ga844b7089e30c37640c8f0fa74c875fed"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafa7a197c87274427b3903a48be33780e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gafa7a197c87274427b3903a48be33780e">XQSPIPS_LQSPI_CR_DUMMY_MASK</a>&#160;&#160;&#160;0x00000700</td></tr>
<tr class="memdesc:gafa7a197c87274427b3903a48be33780e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of dummy bytes between addr and return read data.  <a href="group__qspips.html#gafa7a197c87274427b3903a48be33780e">More...</a><br/></td></tr>
<tr class="separator:gafa7a197c87274427b3903a48be33780e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad327ae631cb6e447615bc9534738af72"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gad327ae631cb6e447615bc9534738af72">XQSPIPS_LQSPI_CR_INST_MASK</a>&#160;&#160;&#160;0x000000FF</td></tr>
<tr class="memdesc:gad327ae631cb6e447615bc9534738af72"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read instr code.  <a href="group__qspips.html#gad327ae631cb6e447615bc9534738af72">More...</a><br/></td></tr>
<tr class="separator:gad327ae631cb6e447615bc9534738af72"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6f187c067994aa193d43051cb5fef0db"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga6f187c067994aa193d43051cb5fef0db">XQSPIPS_LQSPI_CR_RST_STATE</a>&#160;&#160;&#160;0x8000016B</td></tr>
<tr class="memdesc:ga6f187c067994aa193d43051cb5fef0db"><td class="mdescLeft">&#160;</td><td class="mdescRight">Default CR value.  <a href="group__qspips.html#ga6f187c067994aa193d43051cb5fef0db">More...</a><br/></td></tr>
<tr class="separator:ga6f187c067994aa193d43051cb5fef0db"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Linear QSPI Status Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains various status bits of the Linear QSPI controller.</p>
<p>Read/Write. </p>
</div></td></tr>
<tr class="memitem:gaebd63f5db08829210463161a8b2541cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gaebd63f5db08829210463161a8b2541cc">XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gaebd63f5db08829210463161a8b2541cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXI Data FSM Error received.  <a href="group__qspips.html#gaebd63f5db08829210463161a8b2541cc">More...</a><br/></td></tr>
<tr class="separator:gaebd63f5db08829210463161a8b2541cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae1df76d175197557f5341675981b0c6f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gae1df76d175197557f5341675981b0c6f">XQSPIPS_LQSPI_SR_WR_RECVD_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gae1df76d175197557f5341675981b0c6f"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXI write command received.  <a href="group__qspips.html#gae1df76d175197557f5341675981b0c6f">More...</a><br/></td></tr>
<tr class="separator:gae1df76d175197557f5341675981b0c6f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Loopback Delay Adjust Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains various bit masks of Loopback Delay Adjust Register. </p>
</div></td></tr>
<tr class="memitem:ga6d8db4e6ef37984fc65f469d68001ae5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga6d8db4e6ef37984fc65f469d68001ae5">XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:ga6d8db4e6ef37984fc65f469d68001ae5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Loopback Bit.  <a href="group__qspips.html#ga6d8db4e6ef37984fc65f469d68001ae5">More...</a><br/></td></tr>
<tr class="separator:ga6d8db4e6ef37984fc65f469d68001ae5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">SLCR Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Bit Masks of above SLCR Registers . </p>
</div></td></tr>
<tr class="memitem:ga286f17de7ab3285f143c9aab3fc26da4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga286f17de7ab3285f143c9aab3fc26da4">SLCR_LOCK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga286f17de7ab3285f143c9aab3fc26da4"><td class="mdescLeft">&#160;</td><td class="mdescRight">SLCR Write Protection Lock.  <a href="group__qspips.html#ga286f17de7ab3285f143c9aab3fc26da4">More...</a><br/></td></tr>
<tr class="separator:ga286f17de7ab3285f143c9aab3fc26da4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga83fcf6f141c914ab6b8b683fb62232b4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga83fcf6f141c914ab6b8b683fb62232b4">SLCR_UNLOCK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga83fcf6f141c914ab6b8b683fb62232b4"><td class="mdescLeft">&#160;</td><td class="mdescRight">SLCR Write Protection Unlock.  <a href="group__qspips.html#ga83fcf6f141c914ab6b8b683fb62232b4">More...</a><br/></td></tr>
<tr class="separator:ga83fcf6f141c914ab6b8b683fb62232b4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga092a4aa1f062806072ebb1d947708796"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga092a4aa1f062806072ebb1d947708796">LQSPI_RST_CTRL</a>&#160;&#160;&#160;0x00000230</td></tr>
<tr class="memdesc:ga092a4aa1f062806072ebb1d947708796"><td class="mdescLeft">&#160;</td><td class="mdescRight">Quad SPI Software Reset Control.  <a href="group__qspips.html#ga092a4aa1f062806072ebb1d947708796">More...</a><br/></td></tr>
<tr class="separator:ga092a4aa1f062806072ebb1d947708796"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1d7797b08b7b40f62f0dfde3bc8ac547"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga1d7797b08b7b40f62f0dfde3bc8ac547">SLCR_LOCKSTA</a>&#160;&#160;&#160;0x0000000C</td></tr>
<tr class="memdesc:ga1d7797b08b7b40f62f0dfde3bc8ac547"><td class="mdescLeft">&#160;</td><td class="mdescRight">SLCR Write Protection status.  <a href="group__qspips.html#ga1d7797b08b7b40f62f0dfde3bc8ac547">More...</a><br/></td></tr>
<tr class="separator:ga1d7797b08b7b40f62f0dfde3bc8ac547"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5d638bda734baa1b0de6e6994023a3bd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga5d638bda734baa1b0de6e6994023a3bd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XPAR_XSLCR_0_BASEADDR</b>&#160;&#160;&#160;0xF8000000</td></tr>
<tr class="separator:ga5d638bda734baa1b0de6e6994023a3bd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac11ad6eef43004fc003da9fd134c5eac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gac11ad6eef43004fc003da9fd134c5eac">SLCR_LOCK_MASK</a>&#160;&#160;&#160;0x767B</td></tr>
<tr class="memdesc:gac11ad6eef43004fc003da9fd134c5eac"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write Protection Lock mask.  <a href="group__qspips.html#gac11ad6eef43004fc003da9fd134c5eac">More...</a><br/></td></tr>
<tr class="separator:gac11ad6eef43004fc003da9fd134c5eac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaac26206f6af2c9142b6565dcf38d9e74"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gaac26206f6af2c9142b6565dcf38d9e74">SLCR_UNLOCK_MASK</a>&#160;&#160;&#160;0xDF0D</td></tr>
<tr class="memdesc:gaac26206f6af2c9142b6565dcf38d9e74"><td class="mdescLeft">&#160;</td><td class="mdescRight">SLCR Write Protection Unlock.  <a href="group__qspips.html#gaac26206f6af2c9142b6565dcf38d9e74">More...</a><br/></td></tr>
<tr class="separator:gaac26206f6af2c9142b6565dcf38d9e74"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7f208afda8f0b517f00aa56aebe34f39"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga7f208afda8f0b517f00aa56aebe34f39">LQSPI_RST_CTRL_MASK</a>&#160;&#160;&#160;0x3</td></tr>
<tr class="memdesc:ga7f208afda8f0b517f00aa56aebe34f39"><td class="mdescLeft">&#160;</td><td class="mdescRight">Quad SPI Software Reset Control.  <a href="group__qspips.html#ga7f208afda8f0b517f00aa56aebe34f39">More...</a><br/></td></tr>
<tr class="separator:ga7f208afda8f0b517f00aa56aebe34f39"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ga2732af9facd00339b5dc96c83d74a355"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#ga2732af9facd00339b5dc96c83d74a355">XQspiPs_ResetHw</a> (u32 BaseAddress)</td></tr>
<tr class="memdesc:ga2732af9facd00339b5dc96c83d74a355"><td class="mdescLeft">&#160;</td><td class="mdescRight">Resets QSPI by disabling the device and bringing it to reset state through register writes.  <a href="group__qspips.html#ga2732af9facd00339b5dc96c83d74a355">More...</a><br/></td></tr>
<tr class="separator:ga2732af9facd00339b5dc96c83d74a355"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad769e09710e28c9876cebf678f6e890c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspips.html#gad769e09710e28c9876cebf678f6e890c">XQspiPs_LinearInit</a> (u32 BaseAddress)</td></tr>
<tr class="memdesc:gad769e09710e28c9876cebf678f6e890c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initializes QSPI to Linear mode with default QSPI boot settings.  <a href="group__qspips.html#gad769e09710e28c9876cebf678f6e890c">More...</a><br/></td></tr>
<tr class="separator:gad769e09710e28c9876cebf678f6e890c"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
</div><!-- contents -->
</div><!-- doc-content -->
<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
	<p class="footer">&copy; Copyright 2015-2022 Xilinx, Inc. All Rights Reserved.</p>
	<p class="footer">&copy; Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.</p>
</div>
</body>
</html>
